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Showing all articles related to Cu pillar

Copper Pillar Electroplating Tutorial

December 08, 2016

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This tutorial examines the requirements and processing considerations for electroplated copper pillars used in advanced chip packaging applications. The key aspects of the plating process and the role of each in achieving the desired design and performance goals are described.

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Copper Electroplating Fundamentals

November 22, 2016

A short tutorial examining the fundamentals of copper plating

This tutorial examines the concept of copper electroplating and how the process works. It also discusses its use in advanced packaging applications like the dual damascene process, TSV, copper pillars, and copper RDL, as well as how feature geometry as well as plating time affect how additives behave.

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Dow to Present at PRiME 2016: From TSV to Copper Pillars’ Transformative Technology

September 27, 2016

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The Pacific Rim Meeting on Electrochemical and Solid-State Science (PRiME) conference brings together leading industry players to discuss a diverse blend of electrochemical and solid-state science and technology. This year, Dow Electronic Materials will present on how TSV and copper pillars are transforming semiconductor advanced packaging technology.

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Managing Material Properties of Fan-out Wafer-Level Packages

August 30, 2016

RDL Intervia

Advanced packages require specialty electronic materials to be made profitably and reliably. Fan-out wafer level packaging (FOWLP), has three key structures to consider: the dielectric layer, the redistribution layer (RDL), and Cu pillars. Part two of this two-part FOWLP series investigates these key structures and considerations for managing material properties.

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Fast, High-purity Cu Plating Enables Next-Gen Devices

April 20, 2016

Copper (Cu) plating of mega pillar

Fan-out wafer-level packages (FOWLP) are poised for adoption in consumer mobile devices while cloud servers are driving the need for 3DIC packages. Copper (Cu) plating forms critical connections from horizontal redistribution layers (RDLs) through vertical pillars. Learn more about Dow’s approach to optimal Cu plating, as presented at the 2016 IMAPS Device Packaging Conference.

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Three Dow Electronic Materials Technologies Named Finalists for 2015 R&D 100 Awards

August 19, 2015

Dow was recently highlighted as a leading innovator with 21 products selected as finalists for the 2015 R&D 100 Awards. Three of these are technologies developed by Dow Electronic Materials as market-focused solutions and commercialized in the last year.

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Next-Generation Copper, Nickel and Lead-Free Metallization Products for Next-Generation Devices and Applications

August 15, 2015

Meeting the challenging requirements of next-generation devices destined for Internet of Things applications necessitates metallization products that can address fine feature sizes and geometries of today’s advanced chip and package designs. This presentation details how Dow Electronic Materials has optimized its family of advanced electronics packaging metallization products.

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Solving Data Center Reliability Challenges through Packaging

July 07, 2015

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The semiconductor industry is approaching a point where 2.5D and 3D integration technologies will be required to achieve the performance, bandwidth and storage required of next-generation data centers and mobile devices. In this piece, Wataru Tachikawa explores how the entire ecosystem is rolling up its sleeves and working to overcome the remaining challenges.

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