All advanced IC packages, including fan-out wafer-level packages (FOWLP), can only be made profitably and reliably by using specialty electronic materials such as conductors and insulators to form the best electrical connections. It is also essential that those connections be protected from failure due to mechanical shocks or corrosion from environmental factors such as water vapor. In
Part 1 of this 2-part series, we examined the back-story of FOWLP and the markets it serves. Here, we will investigate the key structures used in FOWLP and key considerations for managing their material properties.
Particularly with FOWLP, there are three key structures to consider: the dielectric layer, the redistribution layer (RDL), and Cu pillars. Copper (Cu) metal is used as the main metallic conductor, while nickel functions as a solder barrier, and tin-silver is the industry’s default lead-free (Pb-free) solder. The dielectric material in the RDL provides most of the FOWLP’s environmental protection, and how this dielectric is formed determines its properties.
Figure 1 illustrates concept of a multi-level FOWLP with RDL and megapillars.
Figure 1. Multi-level FOWLP concept
Minimizing mechanical stress in the RDL layers, especially the dielectric material, is essential to FOWLP reliability. If these stresses are not controlled, then the RDL can warp, which affects the planarity of the package. This leads to open ball connections, and in extreme cases, the RDL can crack and delaminate. The dielectric thickness is generally proportional to the height of the copper RDL.
In 40-50% of today’s advanced packages, warpage causes cracking and delamination of the low-K dielectric layers and bonding issues for solder joints, adversely affecting yield. Historically, the curing temperature has been 240-260°C. Since the differences in thermal expansions increase with temperature, lowering the dielectric curing temperature is the best way to minimize warpage and maximize yield. Additionally, since the other essential properties of the final dielectric film—electrical resistance, mechanical strength, etc.—must be maintained, the curing temperature spec may be as low as 180-200°C.
The assembly approach for different FOWLP designs varies and can also impact material requirements. For example, the assembly processes of record for mainstream FOWLP, such as embedded wafer-level ball grid array (eWLB) and reconstituted chip process (RCP), start with placing die face down on a molded wafer and then performing the RDL. So, lower-temperature cure is also critical to maintain the properties of the mold compound. With high-density FOWLP approaches like silicon-less interconnect technology (SLIT), silicon wafer integrated fan-out technology (SWIFT), and the silicon-less integrated module (SLIM), RDL layers are first formed on a sacrificial wafer, and then the die are attached and underfilled, followed by mold. These process flows pose less of a requirement on the cure temperature.
Greater pattern density means finer pitch, and 10-15µm half-pitch lines have already shrunk to just 5µm in high-volume manufacturing, with 2µm in R&D today. Plating these features requires tight with-in die (WID) uniformity (<5%) and doming control (+/-5% TIR) while plating void-free deposits. The typical plating speed required for RDL is 4.5 ASD (1 µm/min) but could go as high as 9 ASD (2 µm/min). Increasing the number of thin layers maintains the overall package height, but new challenges arise with thermo-mechanical and -electrical performance. Thinner layers with smaller structures make the RDL layers even more susceptible to warpage and reliability issues that can develop as a result. Therefore, minimizing mechanical stress in the RDL layers, especially the dielectric material, is increasingly essential to FOWLP reliability as the designs become more complex.
In addition, when L/S shrinks, it means the Cu lines are getting closer together. If the dielectric doesn’t have good physical properties, such as minimal moisture uptake, it can lead to shorts or Cu migration.
Additionally, each layer of dielectric in the RDL must be annealed/cured at a precisely controlled temperature to drive off solvents and cross-link ligands to achieve the final desired material properties, which include high elongation as well as high electrical performance. Why? Because all materials expand and contract at different rates with temperature changes, and the different dielectrics and metals in the package experience different physical stresses during a dielectric curing step. If the polymer is not completely cured, the reaction might not be completed and that can jeopardize mechanical and electric properties. Ideally, these properties can be achieved using a low-temperature process with dielectrics materials that are not brittle.
The challenges of low-temperature cure dielectric design are numerous and include addressing process conditions, such as dispense volume, coating uniformity, film thickness range, photo speed resolution, particle defectivity, purity and cycle time. Thermo-mechanical, electrical and chemical properties, such as glass transition temperature (Tg), coefficient of thermal expansion (CTE), thermal stability, dielectric constant and loss tangent, chemical resistance, and adhesion, must also be managed. Lastly, specific to FOWLP, compatibility issues like spin coating, exposure type, warpage and thermal budget come into play. Low-temperature curing generally results in a drop in mechanical properties, such as modulus, tensile strength and elongation. Achieving these material properties with a low-temperature cure solution while achieving high reliability are the ultimate challenge.
Figure 2. 200µm Megapillar, 25 ASD
In addition to the dielectric layer, the plating processes to form Cu structures within and between RDLs must also evolve to meet the OSAT cost challenges for FOWLP.
Figure 2 shows a scanning electron microscope image of a ~200µm diameter Cu megapillar that would be used to form connections between chip levels in fan-out system-in-package and fan-out package-on-package (see Figure 2 in "Fan-Out Wafer-Level Packaging and Its Material Evolutions" post). For best performance of the package, the WID uniformity for plating 200µm Cu megapillars needs to be <10%, with the ability to control doming within +/-5% at a plating rate of 20 to 40 ASD.
Ideally, it would be most cost-effective to utilize the same Cu solution for both pillar and RDL plating, with the flexibility to plate megapillars at 20 ASD and RDL at 4.5 ASD. Flexibility in plating speeds allows for a single plating chemistry and process that can be used to form Cu features across vast length-scales and that eliminates the need for additional plating tools and associated capital investments. The WID co-planarity of the array, as well as the pillar surface shape of each pillar, is essential to reliability and demonstrates process control between and within pillars, respectively.
For pillars as well as RDL structures, Cu chemistry requirements include the ability to control the pillar and RDL shape, whether it’s a dome, flat, or dished top, but not at the cost of speed or reliability. Bath levelers, suppressors, and accelerators are additives used in the electroplating process to help control the final topography of the structure being plated, as well as control the speed, purity, and quality of the final fill. The leveler additive allows you to shape the final topography of the filled structure. However, some levelers introduce impurities to Cu deposition, so using them requires a balance of achieving desired shape and ensuring reliability. The function of the suppressor is to act as a wetting agent. It wets the wafer surface quickly and aids in controlling plating thickness uniformity. A good wetting agent offers low surface tension and a low contact angle. Finally, the accelerator increases the plating speed and makes bright depositions.
Ultimately, the tunability of Cu pillar and RDL shape provides manufacturers with increased versatility for multiple applications. In addition, higher-purity copper chemistry can reduce manufacturing costs by eliminating the nickel (Ni) barrier between the Cu and solder elements, which is typically required to control topography and eliminate defects in pillars.
Today one of the greatest challenges for a materials provider is accommodating all the varied approaches to FOWLP. As FOWLP continues to find its way into consumer mobile products, OSATs and others working to optimize next-generation FOWLP can rely on Dow’s deep materials engineering expertise to provide the materials to help them achieve these goals.