Dow Electronic Materials

Dow to Present on Acidic CMP Slurry and Advanced Patterning at CSTIC

March 10, 2017


China Semiconductor Technology International Conference (CSTIC) 2017The China Semiconductor Technology International Conference (CSTIC) will be held March 12-13, 2017, in Shanghai, in conjunction with SEMICON China. At this year’s event, Dow will share presentations during the Lithography and Patterning Symposium, as well as the CMP and Post-Polish Cleaning Symposium. Information about these two presentations follow:

A New Acidic ILD Slurry Formulation for Advanced CMP

For advanced interlayer dielectric (ILD) slurries, the requirements are steep. Semiconductor manufacturers are looking for high oxide removal rate, uniformity and planarization; alongside low film defectivity and a competitive cost of ownership. Recent studies demonstrate that an acidic environment for advanced ILD can enable lower abrasives and improved planarization versus a standard fumed silica.

Wenjia (Jessie) Zhou will share from Dow’s research into acidic slurry design. This research led to the development of a new acidic ILD slurry, OPTIPLANE™ 2118. Dow’s OPTIPLANE™ slurry platform for chemical mechanical planarization (CMP) are among Dow’s most advanced slurries for non-metal applications. OPTIPLANE™ 2118 colloidal silica-based slurry was the first product made available for sampling and orders.

A New Acidic ILD Slurry Formulation for Advanced CMP
Monday, March 13, 10:20-10:45
Symposium V: CMP and Post-Polish Cleaning
Yi Guo, Arun Reddy, David Mosley and Robert Auger, Dow Electronic Materials

Material Challenges for Sub 10nm Lithographic Patterning

As semiconductor manufacturers move to advanced nodes, traditional single exposure patterning processes can no longer provide the scaling needed. Exposure tools using the 193 nm wavelength have already reached their resolution limit, and in turn, complex multiple patterning techniques are now being used to enable the required reduction in critical dimensions. The International Technology Roadmap for Semiconductors (ITRS)[1] predicts that 193nm immersion lithography will continue to be extended to advanced nodes as extreme ultraviolet (EUV) lithography technology is not ready. In light of these conditions, as device manufacturers move to the 10 nm node and beyond, a number of challenges arise including cost, reliance on ALD, pitch walking and overlay.

Jim Cameron will share insights into what types of new materials can support advanced patterning processes at these nodes, including barrier layers, advanced photoresists, bottom antireflective coatings (BARCs), silicon antireflective coatings (SiARCs) and spin on carbon (SOC) films. He will also discuss their advantages and some of the benefits each new technology can bring to the manufacturing process.

Material Challenges for Sub 10nm Lithographic Patterning
Monday, March 13, 15:15-15:45
Symposium II: Lithography and Patterning
James Cameron, Dow Electronic Materials

For Further Reading on These Topics

To gain insights into how trends in the semiconductor market led to Dow’s development of the OPTIPLANE™ CMP slurry platform, see this interview with Adam Manzonie, Slurry Business Director for CMP Technologies.

For background on how specialty materials are enabling extensions to 193nm lithographic capabilities, see this interview with representatives of Dow’s Litho Technologies business.

[1] International Technology Roadmap for Semiconductors (ITRS),