Driven primarily by demands from the mobile electronics market, IC substrates need to incorporate more chips in the same size footprint, increasing density and pitch requirements for interconnects and vias. High-end processors are often packaged in flip-chip ball grid arrays (BGAs), and as complexity increases, so does the number of contacts underneath the package.
Substrates in IC packages pose special challenges for very fine lines and concentrated vias. As advanced semiconductor nodes push line width and spacing to 10µm and below, via dimensions are also shrinking. The five-year roadmap projects via diameters will decrease to 50µm according to Prismark and Yole. Along with performance improvements, smaller via dimensions support the growth of 5G development and higher rates of data transmission and exchange. The roadmap also calls for reduction in total package height, creating smaller packages so that more IC units can be mounted. This is especially important for mobile electronics, as smartphones are expected to improve in processing power and add features without increasing the thickness of the device (Figure 1). Any steps that can be taken to reduce total substrate thickness without negatively impacting performance will provide IC substrate suppliers with a competitive advantage.
Figure 1: iPhone moves to thinner dimensions but increased data and performance demands.
There are several bottlenecks that need to be overcome to enable next-generation substrate technologies using an electrolytic plating process. These include via filling ability, plating thickness reduction and uniformity, panel appearance and so on. Among these, reduction of plating thickness distribution across the panel is the most challenging. Fine-pitch BGAs may require more than 1 million vias under the chip, and the entire plated unit thickness should be as uniform as possible across the entire patterned board for maximum reliability. An uneven surface could result in signal transmission loss in fine lines, dimensional distortion of the substrate, and connecting points, such as via and lines, that are short-circuited.
Plating distribution can be quantified by measuring the range in plating thickness across a substrate. The lower the range, the more uniform the plating. Specifications vary depending on the substrate design, but values are trending as low as possible, such as 1µm tolerance for a nominal 18µm plating thickness.
Copper plating suppliers can use multiple approaches to improve the thickness distribution. Increasing flow rate in the plating bath enables more frequent exchange of chemicals, improving current distribution. Adjusting the concentration of inorganic components in the bath, such as sulfuric acid (H2SO4) and copper sulfate (CuSO4) can optimize electrical conductivity. Additives such as brighteners and levelers help improve uniformity. Reducing the overall plating thickness also reduces distribution range, as does reducing the current density. Proper pattern design minimizes extreme fluctuations in uniformity across a substrate.
Unfortunately, however, many of the approaches that improve uniformity also result in lower-quality via filling performance. High flow rate, high H2SO4 concentration and low surface plating thickness are often associated with unreliable or inconsistently filled vias. Many plating chemistries do not perform well in a highly acidic environment, and it can be difficult to completely fill vias while keeping the surface thickness sufficiently low.
Conventional via fill processes tend to result in vias with either bumps or dimples on the top. To minimize or avoid this less desirable shape, and to create flatter, more uniform vias, via filling needs to occur more rapidly at the start of the electroplating process. Faster bottom-up via fill creates vias with a thinner layer of copper plated on the surface while fully filling the vias, reducing the total board thickness. Assuming this can be accomplished without introducing voids, faster filling at the bottom of vias represents a significant improvement over conventional processes with more conformal deposition rates.
Dow has introduced MICROFILL™ SFP copper plating chemistry, which is aimed specifically at IC substrate applications and meets the above goals for improved thickness distribution and enhanced via filling capabilities. MICROFILL™ SFP targets vias that are 25 to 35µm deep and 30 to 50µm wide on patterned boards with line width and spacing in the range of 2 to 20µm.
A combination of optimized brightener, carrier and leveler additives promotes copper deposition at the bottom of the vias while suppressing deposition on the surface. Vias are much flatter than those manufactured using conventional via fill chemistries, as seen in Figure 2. The process can operate successfully at relatively high current densities, improving throughput.
Figure 2: Shape of vias created using various plating chemistries
This latest-generation plating chemistry can achieve much better plating uniformity across a substrate than is possible to attain with conventional plating chemistries. Surface plating can be relatively thin, targeting 12µm, while maintaining consistent via fill. Figures 3 and 4 show a comparison of plating thickness distribution for conventional and SFP processes. Plating is thicker at the edges of the board in all cases, but with SFP, the thickness increase is lower and more uniform across the entire edge.
Figure 3: Graphical thickness distribution for conventional and SFP plating chemistries
Figure 4: Thickness distribution data from conventional and SFP plating chemistries
IC substrate manufacturers need to innovate to remain competitive in a landscape where feature dimensions continue to shrink. Innovation can take many forms, and include advances in both design and materials. Selecting copper plating chemistries optimized for IC substrates is one step manufacturers can take toward achieving their production goals.