When talk turns to interposers, 3D ICs and packaging; fan-out wafer-level packaging and flip chip; and engineered micro systems/devices, such as MEMS/sensors, 3D printing and more, the IMAPS Device Packaging Conference (DPC) must be around the corner.
Organized by the International Microelectronics Assembly and Packaging Society (IMAPS), this international conference is a major forum for the exchange of knowledge among leading experts in advanced device packaging. This year represents the conference’s 14th year, which will be held in Fountain Hills, Arizona, March 5-8, 2018.
Dow Electronic Materials is honored to have its experts and technology featured at two events during the conference. Mark your calendars and be on the lookout for the following presentations:
Growth of Heterogeneous Integration and the Importance of Electronic Materials
Rozalia Beica, Dow Electronic Materials
Keynote Address: Thursday, March 8, 2018, 8:00 – 8:45 a.m.
The next generation of smart devices and applications will continue to drive the need for higher performance, miniaturization and a greater demand for increased functionality. Successful development of next generation packages will require innovative and high performing materials that can be seamlessly integrated, especially considering the increased interest in the industry in system level packaging. Heterogeneous integration of disparate technologies can encompass various packaging platforms, substrates, interconnect and assembly materials. The presentation will focus on market and Advanced Packaging trends, highlighting the various materials required, major challenges for heterogeneous integration and the importance of integration.
Integration of a Chemically Amplified Photoresist and a Panel and Wafer-Level Packaging Stepper for Advanced Packaging Technologies
Joint paper presentation from Rudolph Technologies & Dow Electronic Materials,
Presented by John Mach, Rudolph Technologies
Interactive Poster Session & Happy Hour, Wednesday, March 7, 2018, 5:30 – 6:30 pm
Advanced packaging technologies require materials that will allow for better resolution of patterns associated with the ever-more-challenging device architecture, along with materials that will allow for higher throughput. Device throughput can be increased with imaging materials that have higher sensitivity. Chemically amplified photoresists offer the advantages of excellent sensitivity and resolution with good process margins, coupled with excellent stripping performance and plating bath compatibility for the film thicknesses required in packaging applications.
However, it is the integration of the photomasking material and the availability of today’s advanced back-end exposure tools that allow for improved lithographic imaging. It is this combination that is necessary for meeting the demands of today’s higher resolution and tighter pitch requirements for back-end plating applications, which is essential in producing metallized structures for copper pillar and solder applications. Because the profile of the resist image is directly transferred during the electroplating process, it is critical to have a well-formed image that is resistant to the plating chemistry. Plating bath contamination and resist strippability are other key factors in producing void-free, defect-free structures.
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