Dow Electronic Materials

Dow Litho and CMP Experts to Present Research at SEMICON China’s CSTIC

March 09, 2018

CSTIC 2018 Logo

Dow Electronic Materials will offer two presentations as part of this year’s upcoming China Semiconductor Technology International Conference (CSTIC). CSTIC 2018 will be held March 11-12, in conjunction with SEMICON China in Shanghai.

Now in its 18th year, CSTIC is one of the largest and most comprehensive semiconductor technology conferences in Asia. Organized by SEMI, IMEC and IEEE-EDS, and co-organized by IMECAS, the conference will have nine symposiums covering all aspects of the semiconductor technology with a focus on manufacturing and advanced technology. The conference will tackle several hot topics, including memory, 3D integration and MEMS. Additional focus areas include advanced manufacturing processes, device design, process integration, materials and equipment, emerging semiconductor technologies, circuit design and silicon material applications.

Dow’s team will share research from both its Lithography Technologies and CMP Technologies groups. The first presentation will examine recent developments in advanced patterning materials and embedded barrier layers for 193nm immersion lithography. The second will look at how to optimize chemical mechanical planarization (CMP) pads together with CMP slurries, as well as optimizations at the CMP process level.

Enabling Patterning Materials for Advanced 193nm Immersion Lithography

193nm immersion lithography is still the workhorse of today’s advanced integrated circuit (IC) manufacturing. The ever-increasing throughput of IC manufacturing and increased complexity of photoresist patterning continue to prompt advancement of interfacial property control between immersion water and resist surface. Many in the industry are using an immersion topcoat/resist combination and topcoat-free resists to fulfill these requirements. In addition, novel post-lithography spin-on processes facilitate smaller feature size with improved process window, line width roughness and defectivity.

Cong (Colin) Liu will report on Dow’s progress in developing next-generation patterning materials and embedded barrier layers (EBLs) for positive tone resist. New materials containing EBLs with high static receding contact angle (sRCA) and high dynamic receding contact angle (dRCA) allow for much faster scan speed during exposure. These high contact angle materials offer superior defectivity and equivalent or better lithographic performance as compared with previous generation materials. Colin will also discuss Dow’s progress on a chemical trimming overcoat process as a post-lithography spin-on process that allows for achieving smaller feature size with improved process window, line width roughness and defectivity.

Enabling Patterning Materials for Advanced 193nm Immersion Lithography
Monday, March 12, 15:40-16:00
Symposium II: Lithography and Patterning

Co-optimization of CMP Pad and Slurry for Overall Process Performance Enhancement

CMP continues to be adopted in more process steps and new processes, including in novel applications like through silicon vias (TSVs) and advanced packaging. As usage increases, IC manufacturers are looking for ways to optimize the CMP process to increase performance and optimize cost of ownership. Materials interactions between conditioner, pad and slurry all contribute to overall CMP performance.

In this presentation, Robert (Bob) Auger will discuss considerations in CMP consumables, examining the relationship between CMP pad structure and properties, and offer an overview of considerations for CMP slurry formulation. Then, using an acidic interlayer dielectric (ILD) case study, he will demonstrate that process output parameters are highly multivariate functions of interactions between CMP consumables. Ultimately, if all interactions are taken into account, significantly improved performance can result, allowing manufacturers to de-couple traditionally accepted trade-offs such as defectivity and planarization efficiency.

Co-optimization of CMP Pad and Slurry for Overall Process Performance Enhancement
Monday, March 12, 14:10-14:35
Symposium V: CMP and Post-Polish Cleaning

For Further Reading on These Topics

Learn how new specialty materials are facilitating extensions to 193nm lithographic capabilities in our two-part interview with representatives from Dow’s Litho Technologies business.

For further thoughts on CMP process optimization, read our article on Performance Gains in CMP Slurry for Advanced Semiconductor Nodes by Dow’s Adam Manzonie, Todd Buley, Jia-Ni Chu and Mike Kulus.